Microvia PCB refers to high‑density interconnect (HDI) printed circuit boards adopting microvia technology. Microvias are critical features in modern PCB design, especially for HDI applications. These miniature laser‑drilled holes connect copper traces between PCB layers to enable compact and high‑speed designs.
According to industry standards such as IPC‑2226A, microvia PCB structures are mainly classified into six categories:
1.Type I (1‑stage HDI: 1+N+1)
Structural features: Only the outermost layers contain single‑layer blind microvias, without stacked vias or additional inner buried‑via overlays.
Process characteristics: Single build‑up cycle and single laser‑drilling operation. It delivers the simplest process, highest yield and lowest cost.
Applications: Entry‑level smart terminals and general communication modules.
2.Type II (2‑stage single‑sided stacking: 2+N+1)
Structural features: Two build‑up layers on one side supporting vertical microvia stacking, while the opposite side uses single‑layer blind vias.
Process characteristics: Partial stacked interconnection providing higher routing density than 1‑stage HDI with moderate process complexity.
Applications: Suitable for BGAs with minimum pitch ≥0.35 mm; commonly used in conventional smartphones and tablets.
3.Type III (2‑stage double‑sided stacking: 2+N+2)
Structural features: Two build‑up layers on both top and bottom sides, enabling two‑tier vertical microvia stacking on both outer surfaces.
Process characteristics: Significantly improved routing density to meet requirements of high‑density fine‑pin chip packages.
Applications: Suitable for BGAs with minimum pitch ≥0.30 mm; applied in flagship smartphones, premium wearables and automotive control boards.
4.Type IV (3‑stage HDI: 3+N+3)
Structural features: Three build‑up layers on both sides with three‑tier vertically stacked microvia interconnections.
Process characteristics: Ultra‑high routing density with high manufacturing difficulty. Stringent requirements are imposed on base materials, copper thickness and drilling accuracy.
Applications: Suitable for BGAs with minimum pitch ≥0.25 mm, targeting high‑end products demanding extreme wiring density.
5.Type V (staggered‑microvia any‑layer interconnection)
Structural features: No vertically stacked vias. All microvias are arranged in a staggered pattern to achieve arbitrary inter‑layer connectivity.
Process characteristics: Eliminates typical risks of stacked vias including voids, misregistration and delamination, delivering superior reliability.
Applications: High‑reliability products such as automotive electronics and medical devices.
6.Type VI (fully‑stacked any‑layer interconnection)
Structural features: Vertical stacked‑microvia connections available across all layers; no conventional mechanical through‑holes for ultimate wiring density.
Process characteristics: Compatible with BGAs with minimum pitch ≤0.20 mm. Applied to 5G RF boards, high‑end servers and AI chip substrates.
Note: The symbol “N” denotes the number of layers within the PCB central core, while numerical values represent the count of microvia‑containing build‑up layers.
How Microvias Are Made
Microvia fabrication runs inside the sequential build-up (SBU) cycle, repeated per layer pair: lamination, via formation, via metallization, via filling.
1. Laser drilling. CO₂ lasers ablate the dielectric down to the target copper layer; UV lasers handle finer geometries and can trim to depth with higher precision. Modern systems drill over 100,000 vias per hour and inspect each hole for diameter, roundness, bottom copper exposure and debris immediately after processing.
2. Desmear and cleaning. Laser ablation leaves resin residue on the hole wall. A permanganate or plasma desmear step removes it — a dirty hole wall is the most common root cause of plating adhesion failures.
3. Metallization. An electroless copper seed layer (roughly 0.3–0.5 μm) makes the hole wall conductive, followed by electrolytic copper plating that builds the barrel to the specified thickness.
4. Fill and planarization. Where the design requires it, the via is filled (see next section) and the surface planarized — chemically-mechanically or by overplate-and-polish — so subsequent layers or component pads sit on a flat surface.
Microvia Fill: Four Options and When Each Applies
Fill is not decoration; it is a structural and electrical decision, and the options are not interchangeable:
| Fill method | Typical use |
|---|---|
| Epoxy resin (b-stage) | Filled incidentally during the next lamination cycle |
| Non-conductive / conductive paste | Separate processing step; non-conductive for pure planarization |
| Electroplated copper | Stacked structures needing electrical continuity and current capacity |
| Screen-printed copper paste | Structural fill where plating access is limited |
Two rules govern the decision. First, buried microvias must be filled — there is no later process step that can repair a void inside a buried structure. Second, blind microvias on external layers often need no fill at all, unless something builds on top of them or a component pad sits over them. Copper-filled microvias additionally conduct heat and carry higher current than unfilled ones, which matters under power components.
Why Microvias Fail: The Reliability Physics
Most microvia reliability problems trace to one mechanism: the z-axis coefficient of thermal expansion (CTE) mismatch between the copper metallization in the via and the dielectric around it. As the board heats and cools — every reflow cycle, every power cycle — the dielectric expands several times more than the copper, and the via structure accumulates strain. The energy concentrates at geometry discontinuities, and four failure modes account for nearly all field failures:
- Interfacial separation — the via base detaches from the target pad beneath it
- Barrel cracks — fatigue fracture through the plated via wall
- Corner (knee) cracks — fracture where the barrel meets the surface copper
- Target pad cracks — pull-out of the copper the via lands on
Which of these appears first is not random; it follows the strain concentration at the weakest geometric feature. Statistical analysis (ANOVA) of finite-element fatigue models ranks the controlling design variables: the strain concentration factor dominates, followed by conductor ductility, metallization thickness, and via wall angle. The practical translations: thicker, more ductile copper plating improves life; a tapered wall profile reduces the stress concentration at the base; and geometry that smooths the copper-to-dielectric transition at the knee pays for itself in thermal cycles.
The same physics explains the staggered-versus-stacked reliability gap: stacking concentrates all the layer-transition strain at one x-y location, while staggering distributes it across an area.
Core Design Principles for Microvia PCBs
1.Aspect Ratio Control Principle
Principle: The aspect ratio (ratio of via depth to hole diameter) of microvias shall be kept within 1:1, with an optimal value of 0.75:1 or lower.
Rationale: Given the miniature dimensions of microvias, excessive aspect ratios complicate bottom‑hole cleaning during laser drilling and hinder uniform copper deposition during plating. This tends to create voids or weak interconnections and compromises long‑term reliability.
2.Dimension and Pad Design Principle
Hole‑to‑pad matching: Microvia diameters typically range from 50 μm to 150 μm. Pad sizes shall be at least 0.2 mm larger than the via diameter (e.g., a 0.1 mm via paired with a 0.3 mm pad) to guarantee layer‑to‑layer registration accuracy and a reliable annular‑ring connection.
Pad‑size optimization: Microvia pads may be miniaturized to free additional routing channels, yet they must comply with the fabricator’s minimum annular‑ring requirement, generally ≥0.15 mm.
3.Placement and Stack‑up Design Principle
Stacked versus staggered selection: Microvias can be stacked for space‑saving ultra‑high interconnection density, though strict evaluation of layer‑to‑layer alignment and lamination processes is mandatory.
Alternatively, staggered microvias with lateral offsets deliver superior reliability at the cost of greater area consumption. Trade‑offs shall be made according to routing density and manufacturer process capability. A minimum offset of 0.2 mm is recommended for staggered configurations.
Via‑in‑pad design: Placing microvias directly within component pads saves space and shortens signal paths. Nevertheless, solder‑wicking risks must be carefully assessed to prevent cold joints or solder bridging. Via‑filling or via‑plugging processes shall be adopted when necessary.
4.Signal Integrity and Impedance Control Principle
Minimize interconnection length: Microvias shall be kept as short as practicable; blind vias or single‑stage microvias are preferred. This reduces parasitic inductance and capacitance, mitigates signal reflection and loss, and preserves integrity for high‑speed signals such as millimeter‑wave interfaces.
Impedance matching: Dielectric thickness and pad dimensions surrounding microvias shall be tuned together with stack‑up configuration for impedance control, ensuring matched impedance for high‑speed signals (e.g., 50 Ω).
5.Thermal Management and Current Distribution Principle
Thermal via design: Individual microvias have limited current‑carrying capacity. For high‑power applications, multiple parallel microvias are recommended for current sharing, combined with thermal‑relief patterns.
This prevents localized overheating that could trigger microvia barrel cracking or delamination.
Thermal‑stress mitigation: Microvia designs shall account for Z‑axis coefficient‑of‑thermal‑expansion (CTE) mismatch to avoid delamination between microvias and dielectric materials induced by thermal‑cycling stress.
6.Design‑for‑Manufacturability (DFM) and Process‑Compatibility Principle
Process matching: Microvias are predominantly formed by laser drilling. Designs shall respect laser‑drilling accuracy limits (e.g., ±25 μm) and provide process margin for minimum trace width / trace spacing (e.g., 30 μm). No dimension shall fall below the fabricator’s proven process capability.
Lamination compatibility: Microvia PCBs are manufactured via sequential lamination. Designs shall consider lamination symmetry and dielectric thickness to avoid panel warpage or microvia misalignment caused by uneven pressing pressure.
FAQ
What is a microvia PCB?
A circuit board interconnected through laser-drilled microvias — holes with a 1:1 or lower aspect ratio and depth under 0.25 mm that connect only adjacent layers. Microvias enable the routing density that fine-pitch BGAs and modern HDI stackups require.
What is the difference between a microvia and a regular via?
A regular via is mechanically drilled, spans the full board (or a large core), and typically runs a 6–8:1 aspect ratio. A microvia is laser-drilled, spans one or two layers, and holds a 1:1 aspect ratio — consuming routing space on only the layers it connects.
When does a microvia need to be filled?
Buried microvias always require fill; blind external-layer microvias only need fill when something is built on top of them or a component pad sits over them (via-in-pad). Stacked microvias are copper-filled for electrical continuity through the stack.
Why do microvias crack?
Cyclical thermal expansion of the surrounding dielectric exceeds that of the copper via barrel, and the accumulated strain concentrates at geometric discontinuities — via base, knee, and target pad — until fatigue cracks form. Fill, adequate plating thickness and tapered walls all raise cycle life.
Are stacked or staggered microvias better?
Staggered microvias distribute thermomechanical stress and tolerate more thermal cycles; stacked microvias maximize density and minimize path length but concentrate stress and require copper fill. Most reliability-guided designs stagger where density permits.
Strictly following standardized fabrication processes and scientific design rules effectively prevents common structural failures and improves overall stability. A well‑manufactured microvia pcb delivers outstanding routing density, signal integrity and thermal reliability, fully adapting to the requirements of high‑speed and high‑precision electronic applications.
